Instructions used in general-purpose processors typically include arithmetic instructions. Arithmetic instructions often include two operands that are numbers to be, for example, added to or subtracted from each other. To execute a subtraction instruction using two's complement arithmetic, the subtraction is typically performed in accordance with the identity:A−B=A+not (B)+1where A is a first operand and B is a second operand that is to be subtracted from A. Thus in an arithmetic unit for performing the two's complement subtraction, the B operand is complemented, and a “1” is added (as a “carry in”) to the least significant bit (LSB) of A as well as the complement of B. The addition of the “1” term into the carry in extends the carry-chain of the arithmetic unit and adds a level of complexity that slows down and/or limits the speed at which the instruction can be performed. The carry-chain of this computation is usually part of a timing critical path, especially if the instruction is to be executed in a single cycle, and thus can be limiting to the speed of a processor.